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2.7 v to 5.5 v, serial-input, voltage-output, 12-/16-bit dac ad5512a / ad5542a rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010-2011 analog devices, inc. all rights reserved. features 12-/16-bit resolution 1 lsb inl 11.8 nv/hz noise spectral density 1 s settling time 1.1 nv-sec glitch energy 0.05 ppm/ c temperature drift 5 kv hbm esd classification 0.375 mw power consumption at 3 v 2.7 v to 5.5 v single-supply operation hardware clr and ldac functions 50 mhz spi-/qspi-/microwire-/dsp-compatible interface power-on reset clears dac output to midscale available in 3 mm 3 mm, 10-/16-lead lfcsp and 16-lead tssop applications automatic test equipment precision source-measure instruments data acquisition systems medical and aerospace instrumentation communication equipment general description the ad5512a/ad5542a are single, 12-/16-bit, serial input, unbuffered voltage output digital-to-analog converters (dac) that operate from a single 2.7 v to 5.5 v supply. the dac output range extends from 0 v to v ref and is guaranteed monotonic, providing 1 lsb inl accuracy at 16 bits without adjustment over the full specified temperature range of ?40c to +85c (ad5542a) or ?40c to +125c (ad5512a). offering unbuffered outputs, the ad5512a/ad5542a achieve a 1 s settling time with low offset errors ideal for high speed open loop control. the ad5512a/ad5542a incorporate a bipolar mode of operation that generates a v ref output swing. the ad5512a/ad5542a also include kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. the ad5512a/ad5542a are available in a 16-lead lfcsp with the ad5542a also available in a 10-lead lfcsp and a 16-lead tssop. the ad5512a/ad5542a use a versatile 3-wire interface that is compatible with 50 mhz spi, qspi?, microwire?, and dsp interface standards. functional block diagram 16-bit dac 16-bit dac latch v dd dgnd ldac reff v logic cs din clr v out inv r fb ad5512a/ ad5542a sclk r fb r inv 09199-001 refs a gndf a gnds control logic serial input register figure 1. 16-lead tssop and 16-lead lfcsp 5 6 10 9 16-bit dac 16-bit dac latch serial input regisiter gnd v dd clr ref cs din 1 2 4 v ou t 7 inv 8 r fb ad5542a-1 control logic 3 sclk r fb r inv 09199-002 figure 2. 10-lead lfcsp table 1. related devices part no. description ad5040/ AD5060 2.7 v to 5.5 v 14-/16-bit buffed output dacs ad5541/ ad5542 2.7 v to 5.5 v 16-bit voltage output dacs ad5781/ ad5791 18- / 20-bit voltage output dacs ad5570 16-bit 12 v/15 v bipolar output dac ad5024/ ad5064 4.5 v to 5.5 v, 12- / 16-bit quad channel dac ad5764 16-bit, bipolar, voltage output dac product highlights 1. 16-bit performance without adjustment. 2. 2.7 v to 5.5 v single supply operation. 3. low 11.8 nv/hz noise spectral density. 4. low 0.05 ppm/c temperature drift. 5. 3 mm 3 mm lfcsp and tssop packaging.
ad5512a/ad5542a rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ad5512a ....................................................................................... 3 ad5542a ....................................................................................... 4 ac characteristics ........................................................................ 5 timing characteristics ................................................................ 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and functi on descriptions ............................. 8 typical performance characteristics ........................................... 10 terminology .................................................................................... 14 theory of operation ...................................................................... 15 digital - to - analog section ......................................................... 15 serial interface ............................................................................ 15 unipolar output operation ...................................................... 15 bipolar output operation ......................................................... 16 output amplifier selection ....................................................... 17 force sense amplifier selection ............................................... 17 reference and ground ............................................................... 17 power - on reset .......................................................................... 17 power supply and reference bypassing .................................. 17 applications information .............................................................. 18 micropro cessor interfacing ....................................................... 18 ad5512a/ad5542a to adsp - bf531 interface .................... 18 ad5512a/ad5542a to sport interface .............................. 18 ad5512a/ad5542a to 68hc11/68l11 interface .................... 18 ad5512a/ad5542a to adsp - 2101 interface ....................... 18 ad 5512a/ad5542a to microwire interface .................. 18 layout guidelines ....................................................................... 19 galvanically isolated interface ................................................. 19 decoding multiple dacs .......................................................... 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 21 revision history 5 /11 rev. 0 to rev. a changes to table 3 , power dissipation value and endnote 1 .... 4 changes to table 5 ............................................................................ 6 changes to order ing guide .......................................................... 21 10 /10 revision 0: initial version
ad5512a/ad5542a rev. a | page 3 of 24 s pecifications ad5512a v dd = 2.7 v to 5.5 v , v logic = 2.7 v to 5.5 v, v ref = 2.5 v, agnd = dgnd = 0 v, ?40c < t a < +12 5c, unless otherwise noted. table 2 . parameter 1 min typ max unit test condition static performance resolution 12 bits relative accuracy ( inl ) 0.5 1.0 lsb differe ntial nonlinearity (dnl) 0.5 1.0 lsb guaranteed monotonic gain error +0 . 5 2 lsb gain error temperature coefficient 0.1 ppm/c unipolar zero - code error 0. 0 3 0.5 lsb unipolar zero - code temperature coefficient 0.05 ppm/ c bipolar resisto r matching 1 ?/? r fb /r inv , typically r fb = r inv = 28 k ? 0.02 0.08 % ratio error bipolar zero offset error 0.07 2 lsb bipolar zero temperature coefficient 0.2 ppm/c bipolar zero - code offset error 0.02 0.5 lsb bipolar gain error 0.07 2 lsb bipo lar gain temperature coefficient 0.1 ppm/c output characteristics output voltage range 0 v ref ? 1 lsb v unipolar operation ?v ref + v ref ? 1 lsb v bipolar operation dac output impedance 6.25 k ? tolerance typically 20% power suppl y rejection ratio 1.0 lsb v dd 10% output noise spectral density 11.8 nv/ hz dac code = 0x840 (ad5512a) or 0x8400 (ad5542a) , frequency = 1 khz , u nipolar mode output noise 0.134 v p -p 0.1 hz to 10 hz , u nipolar mode dac reference input 2 reference input range 2.0 v dd v reference input resistance 3 9 k ? unipolar operation 7.5 k ? bipolar operation reference input capacitance 26 pf code 0x0000 26 pf code 0x3 fff logic inputs input current 1 a inpu t low voltage, v inl 0.8 v v dd = 2.7 v to 5.5 v input high voltage, v inh 2.4 v v dd = 2.7 v to 5.5 v input capacitance 2 10 pf hysteresis voltage 2 0.15 v power requirements v dd 2.7 5.5 v all digital inputs at 0 v , v logic , or v dd i dd 125 150 a v ih = v logic or v dd and v il = gnd v logic 1.8 5.5 v i logic 15 24 a all digital inputs at 0 v , v logic , or v dd power dissipation 1.5 6.05 mw 1 temperatures are as follows: a version ?40c to +125c . 2 guaranteed by design, not subject to production test. 3 reference input resistance is code - dependent, minimum at 0x8 55.
ad5512a/ad5542a rev. a | page 4 of 24 ad5542a v dd = 2.7 v to 5.5 v , v logic = 2.7 v to 5.5 v, v ref = 2.5 v, agnd = dgnd = 0 v, ?40c < t a < + 8 5c, unless otherwise noted. table 3 . parameter 1 min typ max unit test condition static performance resolution 16 bits relative accuracy ( inl ) 0.5 1.0 lsb b grade 2.0 a grade differential nonlinearity (dnl) 0.5 1.0 lsb guaranteed monotonic gain error + 0 . 5 2 lsb t a = 25c 3 lsb gain error temperature coefficient 0.1 ppm/c unipolar zero - code error 0.3 0 .7 lsb t a = 25 c 1.5 lsb unipolar zero - code temperature coefficient 0.05 ppm/ c bipolar resistor matching 1.000 ?/? r fb /r inv , typically r fb = r inv = 28 k ? 0.0015 0.0076 % ratio error bipolar zero offset error 1 5 lsb t a = 25 c 6 lsb bipolar zero temperature coefficient 0.2 ppm/c bipolar zero - code offset error 1 5 lsb t a = 25c 6 lsb b ipolar g ain error 1 5 lsb t a = 25c 6 lsb bipolar gain temperature coefficient 0.1 ppm/c output characteristics output voltage range 0 v ref ? 1 lsb v unipolar operation ?v ref +v ref ? 1 lsb v bipolar operation dac output impe dance 6.25 k ? tolerance typically 20% power supply rejection ratio 1.0 lsb v dd 10% output noise spectral density 11.8 nv/ hz dac code = 0x840 (ad5512a) or 0x8400 (ad5542a) , frequency = 1 khz , u nipolar mode output noise 0.134 v p -p 0 .1 hz to 10 hz dac reference input 2 reference input range 2.0 v dd v reference input resistance 3 9 k ? unipolar operation 7.5 k ? bipolar operation reference input capacitance 26 pf code 0x0000 26 pf code 0xffff logic inpu ts input current 1 a input low voltage, v inl 0.8 v v dd = 2.7 v to 5.5 v input high voltage, v inh 2.4 v v dd = 2.7 v to 5.5 v input capacitance 2 10 pf hysteresis voltage 2 0.15 v power requirements v dd 2.7 5.5 v all digital inputs at 0 v, v logic , or v dd i dd 125 150 a v ih = v logic or v dd and v il = gnd v logic 1.8 5.5 v i logic 15 24 a all digital inputs at 0 v, v logic , or v dd power dis sipation 0.625 0.825 mw 1 for 2.7 v v logic 5.5 v, temperatures are as follows: a, b versions ? 40 c to +85 c . 2 guaranteed by design, not subject to production test. 3 reference input resistance is code - dependent, minimum at 0x8555.
ad5512a/ad5542a rev. a | page 5 of 24 ac characteristics v dd = 2.7 v to 5.5 v, v logic = 2.7 v to 5.5 v, 2.5 v v ref v dd , agnd = d g n d = 0 v, ?40c < t a < +12 5 c, unless otherwise noted. table 4 . parameter min typ max unit test condition output voltage settling time 1 s to 1/2 lsb of fs, c l = 10 p f slew rate 17 v/ s c l = 10 pf, m easured from 0% to 63% digital -to - analog glitch impulse 1.1 nv - sec 1 lsb change around major carry reference ?3 db bandwidth 2.2 mhz all 1s loaded reference feedthrough 1 mv p -p all 0s load ed, v ref = 1 v p - p at 100 khz digital feedthrough 0. 2 nv - sec signal -to - noise ratio 92 db spurious free dynamic range 80 db digitally generated sine wave at 1 khz total harmonic distortion 74 db dac code = 0x3fff (ad5512a) or 0xf fff (ad5542a) , frequency 10 khz, v ref = 2.5 v 1 v p -p
ad5512a/ad5542a rev. a | page 6 of 24 timing characteristics v dd = 5 v, 2.5 v v ref v dd , v inh = 90% of v logic , v inl = 10% of v logic , agnd = dgnd = 0 v, unless otherwise noted. table 5. parameter 1, 2 limit 1.8 v logic 2.7 v 3 limit 2.7 v v logic 5.5 v 4 unit description f sclk 14 50 mhz max sclk cycle frequency t 1 70 20 ns min sclk cycle time t 2 35 10 ns min sclk high time t 3 35 10 ns min sclk low time t 4 5 5 ns min cs low to sclk high setup t 5 5 5 ns min cs high to sclk high setup t 6 5 5 ns min sclk high to cs low hold time t 7 10 5 ns min sclk high to cs high hold time t 8 35 10 ns min data setup time t 9 5 4 ns min data hold time (v inh = 90% of v dd , v inl = 10% of v dd ) t 9 5 5 ns min data hold time (v inh = 3 v, v inl = 0 v) t 10 20 20 ns min ldac pulsewidth t 11 10 10 ns min cs high to ldac low setup t 12 15 15 ns min cs high time between active periods t 13 15 15 ns clr pulsewidth 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t f = 1 ns/v and timed from a voltage level of (v inl + v inh )/2. 3 ?40c < t a < +105c. 4 ?40c < t a < +125c. sclk cs din db15 1 db11 2 lda c t 6 t 4 t 12 t 8 t 9 t 2 t 3 t 1 t 7 t 5 t 11 t 10 clr t 13 09199-003 notes 1. for ad5542a = db15. 2. for ad5512a = db11. figure 3. timing diagram
ad551 2a/ad5542a rev. a | page 7 of 24 absolute maximum rat ings t a = 25c , unless otherwise noted . table 6 . parameter rating v dd to agnd ? 0.3 v to +6 v digital input voltage to dgnd ? 0.3 v to v dd + 0.3 v v out to agnd ? 0.3 v to v dd + 0.3 v agndf, agnds to dgnd ? 0.3 v to +0.3 v input current to any pin except supplies 10 ma operating temperature range ad5512a industri al (a version ) ?4 0c to +12 5c ad5542a industri al (a , b versions) ? 40c to +85c storage temperature range ? 65c to +150c maximum junction temperature (t j max) 150c package power dissipation (t j max ? t a )/ ja thermal impedance , ja tssop (ru -16) 113 c/w lfcsp (c p -16-22) 73 c/w lfcsp (c p -10-9 ) 74 c/w lead temperature, soldering peak temperature 1 2 60c esd 2 5 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operat ion of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 as per jedec standard 20. 2 hbm c lassification .
ad5512a/ad5542a rev. a | page 8 of 24 pin configuration an d function descripti ons 09199-036 12 1 1 10 1 3 4 dgnd ldac clr 9 din v out agnds 2 agndf refs 6 cs 5 reff 7 nc 8 sclk 16 r fb 15 v dd 14 v logic 13 inv t op view nc = no connect (not to scale) figure 4 . ad5512a/ad554 2a 16 - lead lfcsp pin configuration 1 ref 2 cs 3 sclk 4 din 5 clr 10 gnd 9 v dd 8 r fb 7 inv 6 v out 09199-034 ad5542a-1 t op view not to scale notes 1. the exposed paddle should be tied to the point of lowest potential, in this case, gnd. figure 5 . ad5542a - 1 10 - lead lfcsp pin config uration table 7 . ad5512a/ad5542a p in f unction d escriptions pin no. 16- lead lfcsp 10- lead lfcsp mnemonic description 1 6 v out analog output voltage from the dac. 2 agndf ground reference point for analog circuitry (force ). 3 agnds ground reference point for analog circuitry (sense). 4 refs voltage reference input (sense) for the dac. connect to an external 2.5 v reference. reference can range from 2 v to v dd . 5 reff voltage reference input (force) for the dac. connect to an external 2.5 v reference. reference can range from 2 v to v dd . 6 2 cs logic input signal. the chip select signal is used to frame the serial data input. 7 nc no connect . 8 3 sclk clock input. data is clocked into th e input register on the rising edge of sclk. duty cycle must be between 40% and 60%. 9 4 din serial data input. this device accepts 16 - bit words. data is clocked into the input register on the rising edge of sclk. 10 5 clr asynchrono us clear input. the clr input is falling edge sensitive. when clr is low, all ldac pulses are ignored. when clr is activated, the dac register is cleared to the model s electable midsca le . 11 ldac ldac input. when this input is taken low, the dac register is simultaneously updated with the contents of the input register. 12 dgnd digital ground. ground reference for digital circuitry. 13 7 inv connection to the internal scaling resistors of the dac. connect the inv pin to the external op amps inverting input in bipolar mode. 14 v logic logic power supply. 15 9 v dd analog supply voltage, 5 v 10%. 16 8 r fb feedback resistor pin. in bipola r mode, connect this pin to the external op amp output. 1 ref voltage reference input for the dac. connect this pin to an external 2.5 v reference. reference can range from 2 v to v dd . 10 gnd ground. epad exposed pad the exposed pad should be ti ed t o the point of lowest potential, in this case , gnd.
ad551 2a/ad5542a rev. a | page 9 of 24 nc = no connect 1 2 3 4 5 6 7 8 v out agndf agnds nc reff refs r fb cs 16 15 14 13 12 1 1 10 9 v logic inv dgnd din sclk clr ldac v dd ad5542a t op view (not to scale) 09199-035 figure 6. ad5542a 16 - lead tssop pin configuration table 8 . ad5542a p in f unction d escriptions pin no. mnemonic description 1 r fb feedback resistor pin . in bipolar mode, connect this pin to the external op amp output. 2 v out analog output voltage from the dac. 3 agndf ground reference point for analog circuitry (force). 4 agnds ground reference point for analog circuitry (sense). 5 refs voltage reference input (sense) for the dac. connect to an external 2.5 v reference. reference can range from 2 v to v dd . 6 reff voltage reference input (force) for the dac. connect to an external 2.5 v reference. reference can range from 2 v to v dd . 7 nc n o connect. 8 cs logic input signal. the chip select signal is used to frame the serial data input. 9 sclk clock input. data is clocked into the input register on the rising edge of sclk. duty cycle must be between 40% and 60%. 10 d in s erial data input. this device accepts 16 - bit words. data is clocked into the input register on the rising edge of sclk. 11 clr asynchronous clear input. the clr input is falling edge sensitive. when clr is low, all ldac pulses are ignored. when clr is act ivated, the dac register is cleared to t he model selectable midscale . 12 ldac ldac input. when this input is taken low, th e dac register is simultaneously updated with the contents of the input register. 13 dgnd digital ground. ground reference for digital circuitry. 14 inv connect ion to the internal scaling resistors of the dac. connect the inv pin to the external op a mps inverting input in bipolar mode. 15 v logic logic power supply. 16 v dd analog supply voltage, 5 v 10%.
ad5512a/ad5542a rev. a | page 10 of 24 typical performance characteristics 0.50 0.25 0 ?0.25 ?0.50 ?0.75 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 code integral nonlinearity (lsb) v dd = 5v v ref = 2.5v 09199-006 figure 7. ad5542a inte gral nonlinearity vs. code 0.25 0 ?0.25 ?0.50 ?0.75 ?1.00 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) integral nonlinearity (lsb) v dd = 5v v ref = 2.5v 09199-007 figure 8. ad5542a integral nonlinearity vs. temperature 0.50 0.25 0 ?0.25 ?0.50 ?0.75 2 3 4 5 6 7 supply voltage (v) linearity error (lsb) v ref = 2.5v t a = 25c dn l in l 09199-008 figure 9. ad5542a linearity error vs. supply voltage 0.50 0.25 0 ?0.25 ?0.50 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 code differential nonlinearity (lsb) v dd = 5v v ref = 2.5v 09199-009 f igure 10 . ad5542a differential nonlinearity vs. code 0.75 0.50 0.25 0 ?0.25 ?0.50 ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) differential nonlinearity (lsb) v dd = 5v v ref = 2.5v 09199-010 figure 11 . ad5542a differential nonlinearity vs. temperature 0.75 0.50 0.25 0 ?0.25 ?0.50 0 1 2 3 4 5 6 reference voltage (v) linearity error (lsb) v dd = 5v t a = 25c dn l in l 09199-011 figure 12 . ad5542a linearity error vs. reference voltage
ad551 2a/ad5542a rev. a | page 11 of 24 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 ?0.7 ?0.8 ?0.9 ?40 25 85 temperature (c) gain error (lsb) v dd = 5v v ref = 2.5v t a = 25c 09199-012 figure 13 . ad5512a/ad5542a gain error vs. temperature 132 116 118 120 122 124 126 128 130 ?40 25 85 temperature (c) supply current (a) v dd = 5v v ref = 2.5v t a = 25c 09199-013 figure 14 . ad5512a/ad5542a supply current vs. temperature 200 0 20 40 60 80 100 120 140 160 180 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 digital input voltage (v) supply current (a) 09199-014 figure 15 . ad5512a/ad5542a supply current vs. digital input voltage 0.15 ?0.15 ?0.10 ?0.05 0 0.05 0.10 ?40 25 85 temperature (c) zero-code error (lsb) v dd = 5v v ref = 2.5v t a = 25c 09199-015 figure 16 . ad5512a/ad5542a zero - code error vs. temperature 0 0.5 1.0 1.5 2.0 0 1 2 3 4 5 6 supp l y current (a) volt age (v) reference voltage v dd = 5v supply voltage v ref = 2.5v t a = 25c 09199-016 fi gure 17 . ad5512a/ad5542a supply current vs . reference voltage or supply voltage 200 150 100 50 0 0 70,000 60,000 50,000 40,000 30,000 20,000 10,000 code (decimal) reference current (a) v dd = 5v v ref = 2.5v t a = 25c 09199-017 figure 18 . ad5512a/ad5542a reference current vs. code
ad5512a/ad5542a rev. a | page 12 of 24 2s/div v ref = 2.5v v dd = 5v t a = 25c din (5v/div) v out (50mv/div) 10 09199-018 100 90 0 figure 19 . ad5512a/ad5542a digital feed through volt age (v) 1.236 1.234 1.232 1.230 1.228 1.226 1.224 ?0.5 0 0.5 1.0 1.5 2.0 5 0 ?5 ?10 ?15 ?20 ?25 ?30 time (ns) v out cs 09199-032 figure 20 . ad5512a/ad5542a digital - to- analog glitch impulse 2s/div v ref = 2.5v v dd = 5v t a = 25c 200pf 10pf 50pf 100pf 100 cs (5v/div) v out (0.5v/div) 09199-020 10 90 0 figure 21 . ad5512a/ad5542a large signal settling time 0.5s/div v ref = 2.5v v dd = 5v t a = 25c 100 v out (1v/div) v out (50mv/div) gain = ?216 1lsb = v ref /(2 n ) ?1 09199-021 10 90 0 figure 22 . ad5512a/ad5542a small signal settl ing time 5 4 3 2 1 0 90 100 110 120 i dd supply (a) hits +125c +25c ?55c 09199-042 figure 23 . ad5512a/ad5542a analog supply current histogram 6 5 4 3 2 1 0 15 16 17 18 19 i logic at rails (a) hits +125c +25c ?55c 09199-043 figure 24 . ad5512a/ad5542a digital supply current histogram
ad551 2a/ad5542a rev. a | page 13 of 24 10 5 0 ?5 0 20 40 60 80 100 120 frequency (hz) output noise (v rms) 09199-037 v dd = 5v v ref = 2.5v t a = 25c data = 0x0000 figure 25 . ad5512a/ad5542a 0.1 hz to 10 hz output noise 40 35 30 25 20 15 10 5 0 600 700 800 900 1000 1200 1100 1300 1400 frequency (hz) noise spectral density (nv rms/ hz) 09199-038 v dd = 5v v ref = 2.5v t a = 25c figure 26 . ad5512a/ad5542a noise spectral density vs. frequency,1 khz 14 12 10 8 6 4 2 0 9600 9700 9800 9900 10,000 10,200 10,100 10,300 10,400 frequency (hz) noise spectral density (nv rms/ hz) 09199-039 v dd = 5v v ref = 2.5v t a = 25c figure 27 . ad5512a/ad5542a noise spectral density vs. frequency, 10 khz 40 20 0 ?20 ?40 ?60 ?80 ?100 0 10,000 20,000 30,000 40,000 60,000 50,000 70,000 frequency (hz) v out (dbm) 09199-040 v dd = 5v v ref = 5v t a = 25c figure 28 . ad5512a/ad5542a total harmonic distortion 10 0 ?20 ?10 ?30 ?40 ?50 ?60 1k 10k 100k 1m 10m 100m frequency (hz) v out /v ref (dbm) 09199-041 v dd = 5v v ref = 2.5v 0.2v figure 29 . ad5512a/ad5542a multiplying bandwidth
ad5512a/ad5542a rev. a | page 14 of 24 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or inl is a measure of the ma ximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl v s. code plot is shown in figure 7 . differential nonlinearity (dnl) dnl is the difference between the measure d change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures mono - tonicity. a typical dnl vs. code plot is shown in f igure 10. gain error gain error is the dif ference between the actual and ideal analog output range, expressed as a percent of the full - scale range. it is the deviation in slope of the dac transfer characteristic from ideal. gain error temperature coefficient gain error temperature coefficient is a measure of the change in gain error with changes in temperature. it is expressed in ppm/c. zero - code error zero - code error is a measure of the output error when zero code is loaded to the dac register. zero - code temperature coefficient this is a measur e of the change in zero - code error with a change in temperature. it is expressed in mv/c. digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes stat e. it is normally specified as the area of the glitch in nv - s ec and is mea sured when the digital input code is changed by 1 lsb at the major carry transition. a digital - to - analog glitch impulse plot is shown in figure 20. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but it is measured when the dac output is not updated. cs power supply rej ection ratio (psrr) is held high while the s clk and din sig nals are toggled. it is specified in nv - s ec and is measured with a full - scale c ode change on the data bus, that is , from all 0s to all 1s and vice versa. a typical digital feedthrough plot is shown in figure 19. psrr indicates how the output of the dac is affected by changes in the power supply voltage. the p ower supply rejection ratio is quoted in t erms of percent change in output per percent change in v dd for full - scale output of the dac. v dd is varied by 10%. reference feedthrough reference feedthrough is a measure of the feedthrough from the v re f input to the dac output when the dac is loaded with all 0s. a 100 khz, 1 v p - p is applied to v ref . reference feedthrough is expressed in mv p - p.
ad551 2a/ad5542a rev. a | page 15 of 24 theory of operation the ad5512a/ad5542a are single, 12- / 16- bit, s erial input, voltage output dac s. they operate from a single supply ranging from 2.7 v to 5 v and consume typically 125 a with a supply of 5 v. data is written to these devices in a 12- b it (ad5512a) or 16- bi t (ad554 2a) word format, via a 3 - or 4 - wire serial interface. to ensure a k nown power - up state , the s e part s are designed with a power - on reset function. in unipolar mode, the output is reset to midscale ; in bipolar mode, the output i s set to 0 v. kelvin sense connections for the reference and analog ground are included on the ad5512a/ ad5542a . digital - to - analog section the dac architecture consists of two matched dac sections. a simplified circuit diagram is shown in figure 30 . the dac architecture of the ad5512a/ad5542a is segment ed. the four msbs of the 16 - bit (ad5542a)/12 - bit (ad5512a) dat a - word are decoded to drive 15 switches, e1 to e15. each switch connects one of 15 matched resistors to either agnd or v ref . the remaining 12 bits of the data - word drive the s0 to s11 switches of a 12 - bit voltage mode r - 2r ladder network. 2r . . . . . s1 . . . . . 2r s1 1 2r e1 2r . . . . . e2 . . . . . 2r 2r s0 2r e15 r r v ref v out 12-bit r-2r ladder four msbs decoded in t o 15 equa l segments 09199-022 figure 30 . dac architecture with this type of dac configuration, the output impedance is independent of code , while the input impedance seen by the reference is heavily code dependent. the output voltage is dependent on the reference voltage , as shown in the following equation : n ref out d v v 2 = w here : d is the decimal data - word loaded to the dac register. n is the resolution of the dac. for a reference of 2.5 v, the equat ion simplifies to the following: 536 , 65 5 . 2 d v out = this gives a v out of 1.25 v with midsc ale loaded, and 2.5 v with full scale loaded to the dac. the lsb size is v ref /65,536. serial interface the ad5512a/ad5542a are controlled by a versati le 3 - or 4 - wire seri al interface that operates at clock rates of up to 5 0 mhz and is compatible with spi, qspi, microwire, and dsp interface standards. the timing diagram is shown in figure 3 . input data is framed by the chip select input, cs . after a high - to - low transition on cs , data is shifted synchronously and latched into the input register on the rising edge of the serial clock, sclk . data is loaded msb first in 12- bit (ad5512a) or 16- bit (ad5542a) words. after 12 (ad5512a) or 16 (ad5542a) data bits have been loaded into the serial input register, a low - to - high transition o n cs transfers the contents of the shift r egister to the dac. data can be loaded to the part only while cs is low. the ad5512a/ad5542a ha ve an ldac function that allows the dac latch to be updated asynchronously by bringing ldac low after cs goe s high. ldac should be maintained high while data is written to the shift register. alternatively, ldac can be tied perma nently low to update the dac synchronously. with ldac tied pe rmanently low, the rising edge of cs load s the data to the dac. unipolar output oper ation these dacs are capable of driving unbuffered loads of 60 k ? . unbu ffered operation results in low supply current, typically 300 a, and a low offset erro r. the ad5512a/ad5542a provide a unipolar output swing ranging from 0 v to v ref . the ad5512a/ad5542a can be config ured to output both unipolar and bipolar voltag es. figure 31 shows a typical unipolar output voltage circuit. the code table for this mode of operation is shown in table 9 . v out refs reff dgnd agndf v dd din sclk ldac cs ad5512a/ ad5542 a ad820/ op196 agnds + 0.1f 0.1f 10f unipolar output externa l op am p 2.5v 5v seria l inter f ace 09199-023 figure 31 . unipolar output tale 9 . ad5542a unipolar code tale dac latch contents msb lsb analog output 1111 1111 1111 1111 v ref (65,535/65,536) 1000 0000 0000 0000 v ref (32,768/65,536) = ? v ref 0000 0000 0000 0001 v ref (1/65,536) 0000 0000 0000 0000 0 v
ad5512a/ad5542a rev. a | page 16 of 24 assuming a perfect reference, the unipolar worst - case output voltage can be calcula ted from the following equation: ( ) inl v v v d v zse ge ref n uni out + + + = ? 2 w here : v out ? uni is the unipolar mode worst - case output . d is the code loaded to dac . n is the resolution of the dac . v ref is the reference voltage applied to the part . v ge is the gain error in volts . v zse is the zero - scale error in vol ts . inl is the integral nonlinearity in volts . bipolar output opera tion with the aid of an external op amp, the ad5512a/ad5542a can be c onfi gured to provide a bipolar volta ge output. a typical circui t is shown in figure 32 . the matched bipolar offset resist ors , r fb and r inv , are connected to an external op amp to achieve this bipolar output swing, typically r fb = r inv = 28 k ? . table 10 shows the transfer function for this output operating mode. also provided on the ad5542 a are a set of kelvin connections to the analog ground inputs. the example includes the adr421 2.5 v reference and the ad8628 low offset and zero - drift reference buffer. table 10. ad5542a bipolar code table dac latch contents msb lsb analog output 1111 1111 1111 1111 +v ref (32,767/32,768) 1000 0000 0000 0001 +v ref (1/32,768) 1000 0000 0000 0000 0 v 0111 1111 1111 1111 ? v ref (1/32,768) 0000 0000 0000 0000 ? v ref (32,768/32,768) = ? v ref assuming a perfect reference, the worst - case bipolar output voltage can be calcula ted from the following equation: a rd rd v rd v v v ref os uni out bip out ) 2 ( 1 )] 1 ( ) 2 )( [( + + + ? + + = ? ? w here : v out ? bip is the bipolar mode worst - case output v out ?uni is the unipolar mode worst - case output . v os is the external op amp input offset voltage. rd is the r fb and r i nv resistor matching error . a is the op amp open - loop gain . v out refs reff inv r fb r inv dgnd agndf v dd din sclk ldac cs ad5512a/ ad5542 a agnds + 0.1f 0.1f 10f bipolar output externa l op am p +2.5v +5v +5v ?5v seria l inter f ace r fb 09199-024 figure 32 . bipolar output
ad551 2a/ad5542a rev. a | page 17 of 24 output amp lifier selection for bipolar mode, a pre cision amplifier should be used and supplied from a dual power supply. this provide s the v ref output. in a single - supply application, selection of a suitable op am p may be more difficult because the output swing of the am pli - fier does not usually include the negative rail, in this case , agnd. this can result in some degradation of the specified per formance unless the application does not use codes near zero . the selected op amp must have a very low - offset voltage (th e dac lsb is 38 v for the ad5542a with a 2.5 v reference) to eliminate the need for output offset trims. input bias current should also be very low because the bias current , multiplied by the dac output impedance ( approximately 6 k ) , adds to the zero - co de error. rail - to - rail input and output performance is required. for fast settling, the slew rate of the op amp should not impede the settling time of the dac. output impedance of the dac is const ant and code - independent, but to minimize gain errors, the input impedance of the output amplifier should be as high as possible. the amplifier should also have a 3 db bandwidth of 1 mhz or greater. the amplifier adds another time constant to the system, thus increasing the settling time of the output. a higher 3 db amplifier bandwidth results in a shorter effective settling time of the combined dac and amplifier . force sense amplifie r selection use single - supply, low - noise amplifiers. a low - output impedance at high frequencies is preferred because the amplifiers must be able to handle dynamic currents of up to 20 ma. reference and ground because the input impedance is code - dependent, the refer - ence pin should be driven from a low impedance source. the ad5512a/ad5542a operate with a voltage reference ranging from 2 v to v dd . references below 2 v r esult in reduced accurac y. the full - scale output voltage of the dac is det ermined by the reference. table 9 and table 10 outline the analog output voltage or partic ular digital codes. for optimum performance, kelvin sense connections are provided on the ad5512a/ad5542a . if the application doesnt require separate force and sense lines, tie the lines close to the package to minimize voltage drops between the package leads and the internal die. power - on reset the ad5512a/ad5542a have a power - on reset function to ensure that the output is at a kno wn state on power - up. on power - up, the dac register contains all 0s until the data is loaded from the serial register. however, th e serial regist er is not cleared on power - up; therefore, its contents are undefined. when loading data i nitially to the dac, 16 bits or more should be loaded to prevent erroneous data appearing on the output. if more than 16 bits are loaded, the last 16 are kept, and if less than 16 bits are loaded, bits remain from the previous word. if the ad5512a/ad5542a must be interfaced with data shorter than 16 bits, the data should be padded with 0s at the lsbs. power supply and ref erence bypassing for accurate h igh - resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 f tantalum capacitor in parallel with a 0.1 f ceramic capacitor.
ad5512a/ad5542a rev. a | page 18 of 24 applications information microprocessor inter facing micropr ocessor interfacing to the ad5512a/ad5542a is via a serial bus that uses standard protocol that is compatible with dsp process ors and microcontrollers. the communications channel requ ires a 3 - or 4 - wire i nterface consisting of a clock signal, a data signal , and a synchronization si gnal. the ad5512a/ad5542a require a 16 - bit data - word with data valid on the rising edge of sclk. th e dac update can be done automatically when all the data is clocked in , or it can be done under the control of the ldac . ad5512a/ad5542a to adsp - bf531 interface the spi interface of the ad5512a/ad5542a is designed to be easily connecte d to industry - standard dsps and micro - controllers. figure 33 shows how the ad5512a/ad5542a can be connected to the analog devices, inc ., blackfin? d s p. the blackfin has an integrated spi port that can be connected directly to the spi pins of the ad5512a/ad5542a . ad5512a/ ad5542a cs sclk din ldac spiselx sck mosi pf9 adsp-bf531 09199-044 figure 33 . ad5512a/ad5542a to adsp - bf531 interface ad5512a/ad5542a to sport interface the analog devices adsp - bf527 has one sport serial port . figure 34 shows how one sp ort interface c an be used to control the ad5512a/ad5542a . 09919-045 ad5512a/ ad5542a cs sclk din ldac sport_tfs sport_tsck sport_d t o gpio0 adsp-bf527 figure 34 . ad5512a/ad5542a to adsp - bf527 interface ad5512a/ad5542a to 68hc11/68l11 inte rface figure 35 shows a serial interface between the ad 5512a/ ad5542a and the 68hc11 /68l11 microcontroller. sck of the 68hc11 /68l11 drives the sclk of the dac, and the mosi out put drives the serial data line serial din. the cs signal is driven from one of the port lines. the 68hc11/68l11 is configured for master mode : mstr = 1, cpol = 0, and cpha = 0. data appearing on the mosi output is valid on the rising edge of sck. ldac cs din sclk pc6 pc7 mosi sck ad5512a/ ad5542a* 68hc 1 1/ 68l 1 1* *additiona l pins omitted for clarit y . 09199-026 figure 35 . ad5512a/ad5542a to 68hc11/68l11 interface ad5512a/ad5542a to adsp - 2101 interface figure 36 shows a serial interface between the ad5512a/ ad5542a and the adsp - 2101. the adsp - 2101 should be set to operate in the sport transmit alternate framing mode. the adsp - 2101 is programmed through the sport control register an d should be configured as follows: internal clock operation, active low framing, 16 - bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. as the data is clocked out on each rising edge of the seri al clock, an inverter is required between the dsp and the da c, because the ad5512a/ad5542a clock data in on the falling edge of the sclk. ldac cs din sclk fo tfs dt sclk ad5512a/ ad5542a* adsp-2101 *additiona l pins omitted for clarit y . 09199-025 figure 36 . ad5512a/ad5542a to adsp - 2101 interface ad5512a/ad5542a to microwire interfa ce figure 37 shows an interface between the ad5512a/ad5542a and any microwire - compatible device. serial data is shifted out on the falling edge of the serial clock and into the ad551 2a/ ad5542a on the rising edge of the serial clock. n o glue logic is required because the dac clocks data into the input shift register on the rising edge. din sclk so sclk ad5512a/ ad5542a* microwire* *additiona l pins omitted for clarit y . cs cs 09199-027 figure 37 . ad5512a/ad5542a to microwire interface
ad551 2a/ad5542a rev. a | page 19 of 24 layout guidelines in any circuit where accuracy is important, careful consi der - ation of the power supply and ground return layout helps to ensure the rated performance. design the printed circuit board (pcb) on which the ad5512a/ad5542a is mounted so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5512a/ad5542a are in a system where multiple devices require an analog ground - to - digital ground connection, make the connection at one point only. establish the star ground point as close as possible to the device. the ad5512a/ad554 2a should have ample supply bypassing of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low ef fective series resistance (esr) and low effective series inductance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. g alvanically i solat ed i nterface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common - mode voltages that may occur . i couple r? products from analog devices provide voltage isolation in excess of 2.5 kv. the serial loadin g structure of the ad5512a/ad5542a makes the parts ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 38 shows a 4 - channel isolated interface to the ad5512a/ad5542a using an adum1400 . for further information, visit http://www.analog.com/icou plers . encode seria l clock in controller adum1400 1 seria l dat a out sync out load dac out decode t o sclk t o din t o cs t o ldac v ia v oa encode decode v ib v ob encode decode v ic v oc encode decode v id v od 1 additiona l pins omitted for clarit y . 09199-046 figure 38 . isolated interface decoding multiple dacs the cs pin of the ad5512a/ad5542a can be used to select one of a number of dacs. all devices receive the same serial clock and serial data, but only one device receive s the cs signal at any one time. the dac addressed is determined by the decoder. there is some digital feedthrough from the digital input lines. using a burst clock minimize s the effects of digital feedthrough on the an alog signal channels. figure 39 shows a typical circuit. ad5512a/ ad5542a cs din sclk v out ad5512a/ ad5542a cs din sclk v out ad5512a/ ad5542a cs din sclk v out ad5512a/ ad5542a cs din sclk v out v dd dgnd en coded address sclk din enable decoder 09199-030 figure 39 . addressing multiple dacs
ad5512a/ad5542a rev. a | page 20 of 24 outline dimensions 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16- 2010-e 1 0.50 bsc b o t t o m v i e w t o p v i e w 1 6 5 8 9 1 2 1 3 4 e x p o s e d p a d pin 1 indica t or 0.50 0.40 0.30 sea ting plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplan arity 0.08 pin 1 indica t or for proper connection of the exposed pad, refer to the pin configuration and functi on descri ption s section of this data sheet. 0.80 0.75 0.70 compliant t o jedec standards mo-220-wee d-6. figure 40 . 16 - lead lead frame chip sc ale package [lfcsp _wq ] 3 mm 3 mm body, very very thin quad (cp - 16 - 22) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 41 . 16 - lead thin shrink small outline package [ tssop] (ru - 16) dimensions shown in millimeters
ad5512a/ad5542a rev. a | page 21 of 24 2.48 2.38 2.23 0.50 0.40 0.30 12100 9-a t op view 1 0 1 6 5 0.30 0.25 0.20 b o t t o m v i e w pin 1 index area sea ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc e x p o s e d p a d 3.10 3.00 sq 2.90 pin 1 indica t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 42 . 10 - lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp - 10 - 9) dimensions shown in millimeters ordering guide model 1 inl dnl power on reset to code temperature range package description package option branding ad5512a acpz - reel7 1 lsb 1 lsb midscale ?40c to +125c 16- lead lfcsp cp - 16- 22 dfq ad5512aacpz - 500r l7 1 lsb 1 lsb midscale ?40c to +125c 16- lead lfcsp cp - 16- 22 dfq ad5542abruz 1 lsb 1 lsb midscale ?40c to +85c 16- lead tssop ru - 16 ad5542abruz - reel7 1 lsb 1 lsb midscale ?40c to +85 c 16- lead tssop ru - 16 ad5542aaruz 2 lsb 1 lsb midscale ?40c to +85c 16- lead tssop ru - 16 ad5542aaruz - reel7 2 lsb 1 lsb midscale ?40c to +85c 16- lead tssop ru - 16 ad5542abcpz - reel7 1 lsb 1 lsb midscale ?40c to +85c 16- lead lfcsp _wq cp - 16- 22 dfl ad5542aacpz - reel7 2 lsb 1 lsb midscale ?40c to +85c 16- lead lfcsp _wq cp - 16- 22 dfk ad5442abcpz - 1 - rl7 1 lsb 1 lsb midscale ?40c to +85c 10- lead lfcsp _wq cp - 10- 9 dfm ad5542abcpz - 500rl7 1 lsb 1 lsb midscale ?40c to +125c 16- lead lfcsp cp - 16- 22 dfl eval - ad554 2 asdz ad5541a evaluation board 1 z = rohs compliant part .
ad5512a/ad5542a rev. a | page 22 of 24 notes
ad5512a/ad5542a rev. a | page 23 of 24 notes
ad5512a/ad5542a rev. a | page 24 of 24 notes ? 2010 - 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09199 - 0 - 5/11(a)

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